Testing of electrical characteristics of an electronic circuit such as IC, LSI and the like formed on a semiconductor wafer for example is performed using a probe card attached to a probe apparatus. The probe card normally has a contactor which supports a large number of probes, and a circuit board connected electrically to the contactor. The contactor is arranged so that a lower face on which the probes are supported faces a wafer, and the circuit board is stacked and arranged on an upper face of the contactor. Testing of electrical characteristics of the wafer is performed by bringing the plurality of probes into contact with electrodes of the electronic circuit on the wafer, and applying an electrical signal for testing from the respective probes to the electrodes of the electronic circuit on the wafer via the circuit board and the contactor.
Conventionally, the plurality of probes described above are joined by ultrasonic bonding, soldering, laser bonding, or the like to connecting terminals exposed on the lower face of the contactor (refer to Patent Document 1). However, when each probe is joined to the contactor as in a conventional manner, it is necessary to join each probe by bringing a bonding tool for joining for example into contact with a joint portion of each of the probes, and thereby a long time is needed for joining all the probes to the contactor. Also, it is necessary to use an apparatus for joining such as the bonding tool, and hence joining of the probes cannot be performed easily. Further, when each probe is joined to the contactor by ultrasonic bonding or soldering as in a conventional manner, in the case where a probe is damaged for example, the probe cannot be detached easily from the contactor, thereby requiring a substantial time for maintenance.
[Patent Document 1] Japanese Patent Application Laid-open No. 2003-215161